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ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 625ksps, 24-bit analog-to-digital converter check for samples: ads1672 1 features description 2 ? ac performance: the ads1672 is a high-speed, high-precision 107db of dynamic range at 625ksps analog-to-digital converter (adc). using an advanced 115.5db of dynamic range at 78ksps delta-sigma ( ) architecture, it operates at speeds up to 625ksps with outstanding ac performance and ? 113db thd dc accuracy. ? dc accuracy: 3ppm inl the ads1672 adc is comprised of a low-drift, 2 m v/ c offset drift chopper-stabilized modulator with out-of-range detection and a dual-path programmable digital filter. 2ppm/ c gain drift the dual filter path allows the user to select between ? programmable digital filter with two post-processing filters: low-latency or user-selectable path: wide-bandwidth. the low-latency filter settles quickly ? low-latency: completely settles in 5.5 m s in one cycle, for applications with large instantaneous changes, such as a multiplexer. the wide-bandwidth ? wide-bandwidth: 305khz bw with flat path provides an optimized frequency response for ac passband measurements with a passband ripple of less than ? flexible read-only serial interface: 0.001db, stop band attenuation of 86db, and a ? standard cmos bandwidth of 305khz. ? serialized lvds the ads1672 is controlled through i/o pins ? there ? easy conversion control with start pin are no registers to program. a dedicated start pin allows for direct control of conversions: toggle the ? out-of-range detection start pin to begin a conversion, and then retrieve ? supply: analog +5v, digital +3v the output data. the flexible serial interface supports ? power: 350mw data readback with either standard cmos and lvds logic levels, allowing the ads1672 to directly connect applications to a wide range of microcontrollers, digital signal processors (dsps), or field-programmable grid arrays ? automated test equipment (fpgas). ? vibration analysis the ads1672 operates from an analog supply of 5v ? sonar and digital supply of 3v, and dissipates 350mw of ? test and measurement power. when not in use, the pdwn pin can be used to power down all device circuitry. the device is fully specified over the industrial temperature range and is offered in a tqfp-64 package. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008 ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. ads1672 ds modulator dvdd dgnd ainp ainn ads1672 agnd avdd vrefp vrefn dual path filter low-latency filter wide-bandwidth filter cmos and lvds compatible serial interface data readydata output serial shift clock chip select interface configuration master clock filter path data rate start conversion power down out-of-range control
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information for the most current package and ordering information, see the package option addendum at the end of this datasheet or see the ti website at www.ti.com . absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted). parameter ads1672 unit avdd to agnd ? 0.3 to +6 v dvdd to dgnd ? 0.3 to +3.6 v agnd to dgnd ? 0.3 to +0.3 v momentary 100 ma input current continuous 10 ma analog i/o to agnd ? 0.3 to avdd +0.3 v digital i/o to dgnd ? 0.3 to dvdd +0.3 v maximum junction temperature +150 c operating temperature range ? 40 to +85 c storage temperature range ? 60 to +150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 electrical characteristics all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. ads1672 parameter test conditions min typ max unit analog inputs . full-scale input voltage v in = (ainp ? ainn) v ref v common-mode input voltage v cm = (ainp + ainn)/2 2.5 v ac performance data rate (f data ) see table 2 ksps inputs shorted together, 105 107 wide-bandwidth path, f data = 625ksps dynamic range db inputs shorted together, wide-bandwidth path, f data = 113 115.5 78.125ksps f in = 10khz, ? 0.5dbfs, 102 wide-bandwidth path, f data = 625ksps f in = 10khz, ? 2dbfs, signal-to-noise ratio (snr) 103 db wide-bandwidth path, f data = 625ksps f in = 10khz, ? 6dbfs, 99 wide-bandwidth path, f data = 625ksps f in = 10khz, ? 0.5dbfs ? 105 total harmonic distortion (thd) f in = 10khz, ? 2dbfs ? 109 db f in = 10khz, ? 6dbfs ? 113 f in = 10khz, ? 0.5dbfs, spurious-free dynamic range (sfdr) ? 120 db signal harmonics excluded dc precision resolution 24 bits 24-bit differential nonlinearity (monotonic) integral nonlinearity input range of 0.5dbfs, t a = +25 c 3 9.5 ppm of fsr offset error ? 2 2 mv offset error drift 2 m v/ c gain error t a = +25 c 1 2 % gain error drift 2 ppm/ c noise see noise performance table ( table 2 ) common-mode rejection at dc 92 db power-supply rejection at dc, avdd 92 db digital filter characteristics (wide-bandwidth path) passband 0 0.424f data hz passband ripple 0.0001 db ? 0.1db attenuation 0.432f data hz passband transition ? 3.0db attentuation 0.488f data hz f clk ? stop band 0.576f data hz 0.576f data stop band attenuation 86 db group delay 28 t drdy settling time see wide bandwidth filter section digital filter characteristics (low-latency path) bandwidth ? 3db attenuation see low-latency filter section settling time complete settling 1 t drdy voltage reference inputs reference input voltage (v ref ) v ref = (vrefp ? vrefn) 2.75 3.0 3.25 v vrefp 2.75 3.0 3.25 v vrefn short to agnd v copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): ads1672
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com electrical characteristics (continued) all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. ads1672 parameter test conditions min typ max unit clock (clk) v ih 0.7avdd avdd v v il agnd 0.3avdd v digital inputs v ih 0.7dvdd dvdd v v il dgnd 0.3dvdd v input leakage dgnd < v in < dvdd 10 m a cmos outputs v oh i oh = 2ma 0.8dvdd v v ol i ol = 2ma 0.2dvdd v lvds outputs steady-state differential output voltage |v od(ss) | 340 mv magnitude change in steady-state differential |v od(ss) | output voltage magnitude between 50 mv logic states steady-state common-mode voltage v oc(ss) 1.2 v output change in steady-state common-mode |v oc(ss) | 50 mv output voltage between logic states peak-to-peak change in common-mode v oc(pp) 50 150 mv output voltage v oy or v oz = 0v 3 ma short-circuit output current (i os ) v od = 0v 3 ma high-impedance output current (i oz ) v o = 0v or +dvdd 5 m a load 5 pf power-supply requirements avdd 4.75 5.0 5.25 v dvdd 2.7 3.0 3.3 v avdd current 51 55 ma cmos outputs, dvdd = 3v 28 32 ma dvdd current lvds outputs, dvdd = 3v 33 37 ma cmos outputs, 350 370 mw avdd = 5v, dvdd = 3v power dissipation power down 5 mw 4 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 device information tqfp package (top view) table 1. terminal functions pin name no. function description 1, 7, 11, 12, 53, avdd analog analog supply 58 2, 3, 6, 9, 10, agnd analog analog ground 54, 56, 57 ainn 4 analog input negative analog input ainp 5 analog input positive analog input rbias 8 analog analog bias setting resistor vcm 13 analog terminal for external bypass capacitor connection to internal common-mode voltage 14, 15, 16, 17, 18, 19, 20, 25, dgnd digital digital ground 26, 31, 47, 50, 51 rsv2 21 reserved short to digital ground rsv1 22 reserved short to digital ground 23, 24, 27, 34, dvdd digital digital supply 48, 49, 52 pdwn 28 digital input power-down control, active low shift-clock source select. sclk_sel 29 digital input if sclk_sel = ' 0 ' , then sclk is internally generated. if sclk_sel = ' 1 ' , then sclk must be externally generated. serial interface select. lvds 30 digital input if lvds = ' 0 ' , then interface is lvds-compatible. if lvds = ' 1 ' , then interface is cmos-compatible. copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads1672 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dvdddgnd drdy drdy doutdout sclksclk rsv3otrd cs start drate[0] drate[1] dvdd fpath 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd agndagnd ainn ainp agnd avdd rbias agndagnd avdd avdd vcm dgnddgnd dgnd vrefp vrefp cap2 vrefn vrefncap1 avdd agnd agnd clk agnd avdd dvdd dgnd dgnd dvdd dgnd dgnd dgnddgnd rsv2 rsv1 dvdd dvdd dgnd dgnd dvdd pdwn sclk _sel lvds dgnd ll_config 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 ads1672
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com table 1. terminal functions (continued) pin name no. function description configure low-latency digital filter. ll_config 32 digital input if ll_config = ' 0 ' , then single-cycle settling is selected. if ll_config = ' 1 ' , then fast-response is selected. digital filter path selection. fpath 33 digital input if fpath = ' 0 ' , then path is wide-bandwidth. if fpath = ' 1 ' , then path is low-latency. drate[1:0] 35, 36 digital input data rate selection start 37 digital input start convert, reset, and synchronization control input cs 38 digital input chip select; active low. otrd 39 digital output digital filter out-of-range indicator rsv3 40 reserved this pin must be left floating. do not connect or short to ground. negative shift clock output. sclk 41 digital output if sclk_sel = ' 0 ' , then sclk is the complementary shift clock output. if sclk_sel = ' 1 ' , then sclk always output is 3-state. positive shift clock output. sclk 42 digital input/output if sclk_sel = ' 0 ' , then sclk is an output. if sclk_sel = ' 1 ' , then sclk is an input. dout 43 digital output negative lvds serial data output dout 44 digital output positive lvds serial data output drdy 45 digital output negative data ready output drdy 46 digital output positive data ready output clk 55 digital input master clock input cap1 59 analog terminal for 1 m f external bypass capacitor vrefn 60, 61 analog negative reference voltage. short to analog ground. cap2 62 analog terminal for 1 m f external bypass capacitor vrefp 63, 64 analog positive reference voltage 6 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 timing characteristics figure 1. data retrieval timing with internal sclk (sclk_sel = 0) timing requirements: internal sclk at t a = ? 40 c to +85 c, and dvdd = 2.7v to 3.3v. symbol description min typ max unit t clk clk period (1/f clk ) 50 ns t clkdr clk to drdy delay 36 ns t drpw drdy pulse width 1 t clk t drsclk internally-generated sclk rising edge to drdy rising edge 4 ns t sclk sclk period (1/f sclk ) 1 t clk t dopd rising edge of sclk to new valid data output (propagation delay) 3 ns t dc clk duty cycle 45 55 % t spwh sclk pulse width high 20 ns copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads1672 clk drdy t clk t sclk sclk internal t drpw t clkdr t dopd t dohd t drsclk dout msb lsb
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com (1) cs may be tied low. figure 2. data retrieval timing with external sclk (sclk_sel = 1) timing requirements: external sclk at t a = ? 40 c to +85 c, and dvdd = 2.7v to 3.3v. symbol description min typ max unit t clk clk period (1/f clk ) 50 ns t clkdr clk to drdy delay 37 ns t drpw drdy pulse width 1 t clk t cssc cs active low to first shift clock (setup time) 5 ns t sclk sclk period (1/f sclk ) 25 ns t spw sclk high or low pulse width 12 ns t dopd rising edge of sclk to new valid data output (propagation delay) 11 ns t sclkdr setup time of drdy rising after sclk falling edge 3 t clk t crsdo cs inactive to data output 3-state 8 ns figure 3. start timing timing requirements: start at t a = ? 40 c to +85 c, and dvdd = 2.7v to 3.3v. symbol description min typ max unit t start_clkr setup time, rising edge of start to rising edge of clk 0.5 t clk t start start pulse width 1 t clk 8 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 start drdy clk t settle t start_clkr t clkdr t start clk drdy t sclk sclk external t drpw t clkdr t cssc t csfdo t spw t spw t dopd t csrdo dout cs (1) msb lsb t clk t sclkdr hi-z
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 typical characteristics all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. output spectrum output spectrum detail view (1k, ? 0.5dbfs signal) (1k, ? 0.5dbfs signal) figure 4. figure 5. output spectrum output spectrum (10k, ? 0.5dbfs signal) (10k, ? 60dbfs signal) figure 6. figure 7. snr and |thd| snr and |thd| vs input frequency vs sampling frequency figure 8. figure 9. copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads1672 0 2040 60 80 100120 140 160 -- - -- - - - amplitude (dbfs) 0 50 100 150 200 250 300 325 frequency (khz) f = 10khz, 60dbfs snr = 45.6dbc thd = 71.6dbc 65,536 points - - in 120115 110 105 100 95 snr, |thd| (dbc) 10 100 1000 frequency (khz) |thd|, ain = 0.5dbfs - snr, ain = 0.5dbfs - 0 5 10 15 20 25 sampling frequency (mhz) 125120 115 110 105 100 95 snr, |thd| (dbc) f = 10khz in snr, ain = 0.5dbfs - |thd|, ain = 0.5dbfs - 0 2040 60 80 100120 140 160 -- - -- - - - amplitude (dbfs) 0 1 2 3 4 5 6 7 8 9 10 frequency (khz) f = 1khz, 0.5dbfs thd = 109.1dbc 65,536 points - - in 0 2040 60 80 100120 140 160 -- - -- - - - amplitude (dbfs) 0 50 100 150 200 250 300 325 frequency (khz) f = 1khz, 0.5dbfs thd = 109.1dbc 65,536 points - - in 0 2040 60 80 100120 140 160 -- - -- - - - amplitude (dbfs) 0 50 100 150 200 250 300 325 frequency (khz) f = 10khz, 0.5dbfs thd = 108.9dbc 65,536 points - - in
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com typical characteristics (continued) all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. snr and |thd| snr and |thd| vs input amplitude vs input common-mode figure 10. figure 11. snr and |thd| noise histogram vs temperature (osr = 32) figure 12. figure 13. 10 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 input common-mode (v) 115110 105 100 95 snr, |thd| (dbc) f = 10khz in |thd|, ain = 6dbfs - snr, ain = 0.5dbfs - snr, ain = 6dbfs - |thd|, ain = 0.5dbfs - 140120 100 8060 40 20 snr, |thd| (dbc) - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 input signal amplitude (dbfs) f = 10khz in |thd| snr 120115 110 105 100 95 snr, |thd| (dbc) f = 10khz in - 40 - 15 10 35 60 85 temperature ( c) |thd|, ain = 6dbfs - snr, ain = 0.5dbfs - snr, ain = 6dbfs - |ths|, ain = 0.5dbfs - - 98 24-bit output code - 126 - 84 - 70 - 14 - 28 - 42 - 56 0 112 98 14 2842 84 70 56 126 - 112 number of occurrences 25002000 1500 1000 500 0 wide bandwidth, f = 625ksps = 27 output codes 65k points input-shorted data s
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 typical characteristics (continued) all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. noise histogram dynamic range vs (osr = 256) oversampling ratio figure 14. figure 15. noise vs inl vs input voltage temperature figure 16. figure 17. copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads1672 116114 112 110 108 106 dynamic range (dbfs) 256 128 64 32 oversampling ration (osr) ll wb 78.125khz: osr = 256156.25khz: osr = 128 312.5khz: osr = 64 625khz: osr = 32 - 40 24-bit output code - 48 - 36 - 32 - 12 - 8 - 4 - 16 - 20 - 24 - 28 04 36 32 8 12 16 28 24 20 4044 48 - 44 number of occurrences 50004500 4000 3500 3000 2500 2000 1500 1000 500 0 wide bandwidth f = 78.125ksps = 10.8 output codes 65k points data s 1412 10 86 4 2 0 rms noise ( v) m - 95 - 76 - 57 - 38 - 19 0 19 38 57 76 95 analog input range ( 100% of fsr) fpath = 0 drate = 11 fpath = 1 drate = 11 fpath = 1 drate = 00 fpath = 0 drate = 00 54 3 2 1 0 1 2 3 4 5 - -- - - integral nonlinearity (ppm) - 3 - 2 - 1 0 1 2 3 analog input voltage (v) +85 c +25 c - 40 c
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com typical characteristics (continued) all specifications are at t a = ? 40 c to +85 c, avdd = 5v, dvdd = 3v, f clk = 20mhz, v ref = +3v, and r bias = 7.5k ? , unless otherwise noted. |thd| snr vs r bias vs r bias figure 18. figure 19. power vs r bias figure 20. 12 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 104102 100 9896 94 92 90 snr (dbc) 0 10 20 30 40 50 60 70 r (k ) w bias f = 2.5mhz clk f = 10mhz clk f = 20mhz clk f = 10khz, ain = 0.6dbfs - in 115110 105 100 |thd| (dbc) 5 10 15 20 25 30 35 40 45 50 55 60 65 r (k ) w bias f = 20mhz clk f = 10mhz clk f = 2.5mhz clk f = 10khz, ain = 0.5dbfs in - 500450 400 350 300 250 200 150 100 50 power (mw) 5 10 15 20 25 30 35 40 45 50 55 60 65 r (k ) w bias f = 20mhz clk f = 10mhz clk f = 2.5mhz clk f = 10khz, ain = 0.5dbfs in -
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 overview the ads1672 is a 24-bit, analog-to-digital a dedicated start pin allows precise conversion converter (adc). it provides high-resolution control; toggle the pin to begin the conversion measurements of both ac and dc signals and features process. the ads1672 is configured by setting the an advanced multi-stage analog modulator with a appropriate i/o pins ? there are no registers to programmable and flexible digital decimation filter. program. data are retrieved over a serial interface that can support either cmos or lvds voltage figure 21 shows a block diagram of the ads1672. levels. in addition, the serial interface can be the modulator is chopper-stabilized for low-drift internally or externally clocked. this flexibility allows performance and measures the differential input direct connection to a wide range of digital hosts signal v in = (ainp ? ainn) against the differential including dsps, fpgas, and microcontrollers. reference v ref = (vrefp ? vrefn). the digital filter receives the modulator signal and processes it a detection circuit monitors the conversions to through the user-selected path. the low-latency path indicate when the inputs are out-of-range for an provides single-cycle settling, and is ideal when using extended duration. a power-down pin ( pdwn) shuts a multiplexer or when measuring large transients. the off all circuitry when the ads1672 is not in use. wide-bandwidth path provides outstanding frequency x response with very low passband ripple, a steep transition band, and large stop band attenuation. this x path is well-suited for applications that require high-resolution measurements of high-frequency ac x signal content. figure 21. ads1672 block diagram copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads1672 biasing rbias cap1 cap2 ainp ainn vcm cs lvds otrd fpath drate[1:0] ll_config ads1672 sclk_sel ds modulator dvdd dgnd agnd avdd vrefp vrefn dual path filter low-latency filter wide-bandwidth filter cmos- and lvds- compatible serial interface and control v in v ref sclk, sclk dout, dout drdy, drdy clk start pdwn s s
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com noise performance analog inputs (ainp, ainn) the ads1672 offers outstanding noise performance the ads1672 measures the differential signal, that can be optimized by adjusting the data rate. as v in = (ainp ? ainn), against the differential the averaging is increased (thus reducing the data reference, v ref = (vrefp ? vrefn). the most rate), the noise drops correspondingly. table 2 shows positive measurable differential input is v ref , which the noise as a function of data rate for both the produces the most positive digital output code of low-latency and the wide-bandwidth filter paths under 7fffffh. likewise, the most negative measurable the conditions shown. differential input is ? v ref , which produces the most negative digital output code of 800000h. table 2 lists some of the more common methods of specifying noise. the dynamic range is the ratio of analog inputs must be driven with a differential signal the root-mean-square (rms) value of a full-scale sine to achieve optimum performance. the recommended wave to the rms noise with the inputs shorted common-mode voltage is 2.5v. the ads1672 together. this value is expressed in decibels relative samples the analog inputs at very high speeds. it is to full-scale (dbfs). the input-referred noise is the critical that a suitable driver be used. see the rms value of the noise with the inputs shorted, application information section for recommended referred to the input of the ads1672. the effective circuit designs. number of bits (enob) is calculated from a dc the ads1672 uses a switched-capacitor circuitry to perspective using the formula in equation 1 , where measure the input voltage. internal capacitors are full-scale range equals 2v ref . charged by the inputs and then discharged internally with each clock (clk) cycle. figure 22 shows the effective input impedance seen by the driving amplifier. (1) noise-free bits specifies noise, again from a dc perspective using equation 1 , with peak-to-peak noise substituted for rms noise. figure 22. effective input impedance table 2. noise performance (1) data dynamic input-referred noise-free filter path rate[1:0] data rate range noise enob bits 00 36ksps 115db 3.9 m v rms 20.6 17.8 low-latency 01 68ksps 113db 5.0 m v rms 20.2 17.5 (single-cycle settling 10 120ksps 110db 6.7 m v rms 19.8 17.1 configuration) 11 180ksps 108db 8.9 m v rms 19.4 16.7 00 78.1ksps 115.5db 3.9 m v rms 20.6 17.8 01 156.3ksps 113db 5.0 m v rms 20.2 17.5 wide-bandwidth 10 312.5ksps 110db 6.8 m v rms 19.8 17.0 11 625.0ksps 107db 10.1 m v rms 19.2 16.5 (1) v ref = 3v, f clk = 20mhz. 14 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 full-scale range rms noise ln(2) enob = ln z = 3.125k w eff 20mhz f clk ( ( ainp ainn
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 voltage reference inputs conversion start (vrefn, vrefp) the start pin provides an easy and precise the voltage reference for the ads1672 is the conversion control. to perform a single conversion, differential voltage between vrefp and vrefn: pulse the start pin as shown in figure 23 . the start signal is latched internally on the rising edge v ref = (vrefp ? vrefn) (2) of clk. multiple conversions are performed by a high-quality reference voltage with the appropriate continuing to hold start high after the first drive strength is essential for achieving the best conversion completes; see the digital filter performance from the ads1672. noise and drift on descriptions for more details on multiple conversions, the reference degrade overall system performance. because the timing depends on the filter path see the application information section for reference selected. circuit examples. a conversion can be interrupted by issuing another it is recommended that a minimum 10 m f and 0.1 m f start pulse before the ongoing conversion ceramic bypass capacitors be used directly across completes. when an interruption occurs, the data for the reference inputs, vrefp and vrefn. these the ongoing conversion are flushed and a new capacitors should be placed as close as possible to conversion begins. drdy indicates that data are the device under test for optimal performance. ready for retrieval after the filter has settled, as shown in figure 24 . common-mode voltage (vcm) the vcm pin outputs a voltage of avdd/2 and can be used to set the common-mode output of the circuitry that drives the ads1672. the pin must be bypassed with a 1 m f capacitor placed close to the package pin, even if it is not connected elsewhere. the vcm pin has very little drive capability and should not be used to drive any loads. figure 23. start pin used for single conversions (1) see low-latency filter section and wide bandwidth filter section for specific values of settling time t settle . figure 24. example of restarting a conversion with start copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads1672 start drdy clk t start t settle (1) t settle (1) t start_clkr ongoing conversion flushed;new conversion started start drdy clk t start t settle (1) t start_clkr
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com digital filter low-latency digital filter in delta-sigma adcs, the digital filter has a critical the low-latency (ll) filter provides a fast settling influence on device performance. the digital filter response targeted for applications that need sets the frequency response, data rate, bandwidth, high-precision measurements with minimal latency. a and settling time. choosing to optimize some of these good example of this type of application is using a features in a filter means that compromises must be multiplexer to measure multiple inputs. the faster that made with other specifications. these tradeoffs the adc settles, the faster the measurement can determine the applications for which the device is complete and the multiplexer can advance to the next best suited. input. the ads1672 offers two digital filters on-chip, and the ads1672 ll filter supports two configurations to allows the user to direct the output data from the help optimize performance for these types of modulator to either the wide-bandwidth or applications. low-latency filter. these filters allow the user to use the ll_config input pin selects the configuration, one converter design to address multiple applications. as shown in table 4 . be sure to strobe the start the low-latency path filter has minimal latency or pin after changing the configuration. if a conversion is settling time. this path is ideal for measurements with in process during a configuration change, the output large, quick changes on the inputs (for example, data for that conversion are not valid and should be when using a multiplexer). the low-latency discarded. characteristic allows the user to cycle through the multiplexer at high speeds. the frequency table 4. low-latency pin configurations characteristics are relaxed in order to provide the low low-latency latency. ll_config pin configuration the other path provides a filter with excellent 0 single-cycle settling frequency response characteristics. the passband 1 fast response ripple is extremely small, the transition band is very steep, and there is large stop band attenuation. the first configuration is single-cycle settling . as the these characteristics are needed for high-resolution name implies, this configuration allows for the filter to measurements of ac signals. the tradeoff here is that completely settle in one conversion cycle; there is no settling time increases; but for signal processing, this need to discard data. each data output is comprised increase is not generally a critical concern. of information taken during only the previous conversion. the drate[1:0] digital input pins select the fpath digital input pin sets the filter path the data rate for the single-cycle settling selection, as shown in table 3 . note that the start configuration, as shown in table 5 . note that the pin must be strobed after a change to the filter path start pin must be strobed after a change to the selection or data rate. if a conversion is in process data rate. if a conversion is in process during a data during a filter path or data rate change, the output rate change, the output data for that conversion are data are not valid and should be discarded. not valid and should be discarded. table 3. ads1672 filter path selection blank fpath pin selected filter path blank 1 low-latency path 0 wide-bandwidth path table 5. low-latency data rates with single-cycle settling configuration drate[1:0] data rate (1/t drdy-scs ) settling time, t settle-ll ? 3db bandwidth (1) 00 36.30ksps 27.55 m s 550 t clk 34khz 01 67.80ksps 14.75 m s 294 t clk 68khz 10 119.76ksps 8.35 m s 166 t clk 130khz 11 180.18ksps 5.55 m s 110 t clk 215khz (1) the input signal aliases when its frequency exceeds f data /2, in accordance with the nyquist theorem. 16 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 the second configuration is fast response . the figure 25 illustrates the response of both drate[1:0] digital input pins select the data rate for configurations on approximately the same time scale the fast response configuration, as shown in in order to highlight the differences. with the table 6 . when selected, this configuration provides a single-cycle settling configuration, each conversion higher output data rate. the faster output data rate fully settles; in other words, the conversion period allows for more averaging by a post-processor within t drdy-scs = t settle-ll . the benefit of this configuration a given time interval to reduce noise. it also provides is its simplicity ? the ads1672 functions similar to a a faster indication of changes on the inputs when sar converter and there is no need to consider monitoring quickly-changing signals (for example, in a discarding partially-settled data because each control loop application). conversion is fully settled. with the fast response configuration, the data rate for table 6. low-latency data rates with conversions after initial settling is faster; that is, the fast-response configuration conversion time is less than the settling: drate data rate settling time, ? 3db t drdy-fr < t settle-ll . one benefit of this configuration [1:0] (1/t drdy-fr ) t settle-ll bandwidth is a faster response to changes on the inputs, 00 78.125ksps 27.55 m s 550 t clk 34khz because data are supplied at a faster rate. another 01 156.25ksps 14.75 m s 294 t clk 68khz advantage is better support for post-processing. for example, if multiple readings are averaged to reduce 10 312.5ksps 8.35 m s 166 t clk 130khz noise, the higher data rate of the fast response 11 625ksps 5.55 m s 110 t clk 215khz configuration allows this averaging to happen in less time than it requires with the single-cycle settling settling time filter. a third benefit is the ability to measure higher input frequencies without aliasing as a result of the the settling time in absolute time ( m s) is the same for higher data rate. both configurations of the low-latency filter, as shown in table 5 and table 6 . the difference between the configurations is seen with the timing of the conversions after the filter has settled from a pulse on the start pin. note: drdy scs is the drdy output with the low-latency single-cycle settling configuration. drdy fr is the drdy output with the low-latency fast-response settling configuration. figure 25. low-latency single-cycle settling and fast-response configuration conversion timing copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads1672 t settle-ll t drdy-fr t drdy-scs settle-ll = t start clk t start_clkr t clkdr drdy scs drdy fr
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com it is important to note, however, that the absolute settling time of the low-latency path does not change when using the fast response configuration. changes on the input signal during conversions after the initial settling require multiple cycles to fully settle. to help illustrate this requirement, consider a change on the inputs as shown in figure 29 , where start is assumed to have been taken high before the input voltage was changed. the readings after the input change settle as shown in figure 26 . conversion 3 provides a fully-settled result at the new v in signal. figure 27. frequency response of low-latency filter in fast-response configuration figure 26. step response for low-latency filter with fast-response configuration frequency response figure 27 shows the frequency response for the figure 28. extended frequency response of low-latency filter path normalized to the output data low-latency path rate, f data . the overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency. figure 28 shows the response with the fastest data rate selected (625ksps when f clk = 20mhz). note: start pin held high previous to change on analog inputs. figure 29. settling example with the low-latency filter in fast-response configuration 18 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 0 2040 60 80 100120 -- - - -- - 140 magnitude (db) 0 1 2 frequency (f /f ) in clk 3 data 1 data 2 data 3 data 4 data 0 v in drdy ll-fr change onanalog inputs fully-settled data available 0 1020 30 40 50 60 -- - - - - - - 7080 magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (f /f ) in data drate[1:0]= 00 drate[1:0]= 11 120100 8060 40 20 0 settling (%) 0 1 2 3 4 conversions (1/f ) drdy-fr
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 phase response the low-latency filter uses a multiple stage linear phase digital filter. linear phase filters exhibit constant delay time versus input frequency (also know as constant group delay ). this feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency. this behavior results in essentially zero phase error when measuring multi-tone signals. wide-bandwidth filter the wide-bandwidth (wb) filter is well-suited for measuring high-frequency ac signals. this digital filter figure 30. frequency response of offers excellent passband and stop band wide-bandwidth filter characteristics. blank the drate[1:0] digital input pins select from the four data rates available with the wb filter, as shown in table 7 . note that the start pin must be strobed after a change to the data rate. if a conversion is in process during a data rate change, the output data for that conversion are not valid and should be discarded. table 7. wide-bandwidth data rates drate data rate ? 3db settling time, [1:0] (1/t drdy-wb ) bandwidth t settle-wb 00 78.125ksps 38khz 704 m s 14061 t clk 01 156.25ksps 76khz 352 m s 7033 t clk 10 312.50ksps 152khz 176 m s 3519 t clk 11 625.0ksps 305khz 88 m s 1762 t clk figure 31. passband response for while using the wide-bandwidth filter path, the wide-bandwidth filter ll_config pin must be set to logic high. setting ll_config to a logic low forces the ads1672 to switch to the low-latency filter path, single cycle settling mode overriding fpath pin. frequency response figure 30 shows the frequency response for the wide-bandwidth filter path normalized to the output data rate, f data . figure 31 shows the passband ripple, and the transition from passband to stop band is illustrated in figure 32 . these three plots are valid for all of the data rates available on the ads1672. simply substitute the selected data rate to express the x-axis in absolute frequency. figure 32. transition band response for wide-bandwidth filter copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads1672 20 0 2040 60 80 100 -- - - -- - 120140 magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (f /f ) in data 0.000050.00005 0.00015 0.00025 0.00035 -- - - magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 normalized frequency (f /f ) in data 20 2 4 6 8 10 -- - - - magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 normalized frequency (f /f ) in data
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com settling time the overall frequency response repeats at the modulator sampling rate, which is the same as the the wide-bandwidth filter fully settles before input clock frequency. figure 33 shows the response indicating data are ready for retrieval after the start with the fastest data rate selected (625ksps when pin is taken high, as shown in figure 35 . for this f clk = 20mhz). filter, the settling time is larger than the conversion time: t settle-wb > t drdy-wb . instantaneous steps on the input require multiple conversions to settle if start is not pulsed. figure 34 shows the settling response with the x-axis normalized to conversions or data-ready cycles. the output is fully settled after 55 data-ready cycles. figure 33. extended frequency response of wide-bandwidth path phase response the wide-bandwidth filter uses a multiple-stage, linear-phase digital filter. linear phase filters exhibit figure 34. step response for constant delay time versus input frequency (also wide-bandwidth filter know as constant group delay ). this feature means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency. this behavior results in essentially zero phase error when measuring multi-tone signals. (1) t drdy = 1/f data . see table 7 for the relationship between t settle and t drdy when using the wide-bandwidth filter. figure 35. start pin used for multiple conversions with wide-bandwidth filter path 20 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 0 50 100150 - -- magnitude (db) 0 frequency (f / in f clk) 1 2 3 120100 8060 40 20 0 20 - settling (%) 0 10 20 30 40 50 60 conversions (1/t ) drdy-wb fully settled at 55 conversions start drdy t drdy (1) t drdy t drdy t drdy clk t settle t start_clkr
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 otrd function when using lvds, the cs function is not available and sclk must be internally generated. the states of the ads1672 provides an out-of-range (otrd) pin the cs and sclk_sel pins are ignored, but do not that can be used in feedback loops to set the leave these pins floating; they must be tied high or dynamic range of the input signal. low. the otrd function is triggered when the output code of the digital filter exceeds the positive or negative using cmos output swings full-scale range. otrd goes high on the rising edge when the lvds pin is set to '1', the ads1672 of drdy. when the digital output code returns within outputs are cmos-compliant and swing from rail to the full-scale range, otrd returns low on the next rail. the data out and data ready signals are output rising edge of drdy. otrd can also be used when on the differential pairs of pins dout/ dout and small out-of-range input glitches must be ignored. drdy/ drdy, respectively. note that these are the same pins used to output lvds signals when the serial interface lvds pin is set to '0'. dout and drdy are complementary outputs provided for convenience. the ads1672 offers a flexible and easy-to-use, when not in use, these pins should be left floating. read-only serial interface designed to connect to a wide range of digital processors, including dsps, see the serial shift clock section for a description of microcontrollers, and fpgas. the ads1672 serial the sclk and sclk pins. interface can be configured to support either standard cmos voltage swings or low-voltage differential data output (dout, dout) swings (lvds). in addition, when using standard cmos voltage swings, sclk can be internally or data are output serially from the ads1672, msb first, externally generated. on the dout and dout pins. when lvds signal swings are used, these two pins act as a differential the ads1672 is entirely controlled by pins; there are pair to produce the lvds-compatible differential no registers to program. connect the i/o pins to the output signal. when cmos signal swings are used, appropriate level to set the desired function. the dout pin is the complement of dout. if dout whenever changing the i/o pins that are used to is not used, it should be left floating. control the ads1672, be sure to issue a start pulse immediately after the change in order to latch data ready (drdy, drdy) the new values. data ready for retrieval are indicated on the drdy using lvds output swings and drdy pins. when lvds signal swings are used, these two pins act as a differential pair to produce the when the lvds pin is set to '0', the ads1672 lvds-compatible differential output signal. when outputs are lvds tia/eia-644a compliant. the data cmos signal swings are used, the drdy pin is the out, shift clock, and data ready signals are output on complement of drdy. if one of the data ready pins is the differential pairs of pins dout/ dout, not used when cmos swings are selected, it should sclk/ sclk, and drdy/ drdy, respectively. the be left floating. voltage on the outputs is centered on 1.2v and swings approximately 350mv differentially. for more information on the lvds interface, refer to the document low-voltage differential signaling (lvds) design notes (literature number slla014 ) available for download at www.ti.com . copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads1672
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com serial shift clock (sclk, sclk, exceeding full-scale. table 9 summarizes the ideal sclk_sel) output codes for different input signals. when the input is positive out-of-range, exceeding the positive the serial shift clock sclk is used to shift out the full-scale value of v ref , the output clips to all conversion data, msb first, onto the data output 7fffffh. likewise, when the input is negative pins. either an internally- or externally-generated shift out-of-range by going below the negative full-scale clock can be selected using the sclk_sel pin. if value of ? v ref , the output clips to 800000h. sclk_sel is set to '0', a free-running shift clock is generated internally from the master clock and table 9. ideal output code vs input signal outputs on the sclk and sclk pins. the lvds pin input signal determines if the output voltages are cmos or lvds. v in = (ainp ? ainn) ideal output code (1) if sclk_sel is set to '1' and lvds is set to '1', the v ref 7fffffh sclk pin is configured as an input to accept an externally-generated shift clock. in this case, the 000001h sclk pin always outputs low. when sclk_sel is set to '0', the sclk and sclk pins are configured as 0 000000h outputs, and the shift clock is generated internally using the master clock input (clk). ffffffh when lvds signal swings are used, the shift clock is automatically generated internally regardless of the state of sclk_sel. in this case, sclk_sel cannot 8000000h be left floating; it must be tied high or low. (1) excludes effects of noise, inl, offset and gain errors. table 8 summarizes the ads1672 supported serial clock configurations. clock input (clk) table 8. supported serial clock configurations the ads1672 requires that an external clock signal digital outputs shift clock (sclk) be applied to the clk input pin. the sampling of the modulator is controlled by this clock signal. as with lvds must be generated internally any high-speed data converter, a high-quality clock is internal (sclk_sel = '0') cmos essential for optimum performance. crystal clock external (sclk_sel = '1') oscillators are the recommended clk source; other sources, such as frequency synthesizers, are usually chip select ( cs) inadequate. make sure to avoid excess ringing on the clk input; keep the trace as short as possible. the chip select input ( cs) allows multiple devices to share a serial bus. when cs is inactive (high), the measuring high-frequency, large amplitude signals serial interface is reset and the data output pins requires tight control of clock jitter. the uncertainty dout and dout enter a high-impedance state. during sampling of the input from clock jitter limits the sclk is internally generated; the sclk and sclk maximum achievable snr. this effect becomes more output pins also enter a high-impedance state when pronounced with higher frequency and larger cs is inactive. the drdy and drdy outputs are magnitude inputs. fortunately, the ads1672 always active, regardless of the state of the cs oversampling topology reduces clock jitter sensitivity output. cs may be permanently tied low when the over that of nyquist rate converters, such as pipeline outputs do not share a bus. and successive approximation converters, by at least a factor of 32. data format for best performance, the duty cycle of clk should the ads1672 outputs 24 bits of data in two ? s be very close to 50%. the rise and fall times of the complement format. a positive full-scale input clock should be less than 2ns and the clock produces an output code of 7fffffh, and the amplitude should be equal to avdd. negative full-scale input produces an output code of 800000h. the output clips at these codes for signals 22 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 + v 2 1 ref - 23 - v 2 1 ref - 23 - v ref 2 2 1 - 23 23 ( ) <
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 synchronizing multiple ads1672s analog power dissipation the start pin should be applied at power-up and an external resistor connected between the rbias resets the ads1672 filters. start begins the pin and the analog ground sets the analog current conversion process, and the start pin enables level, as shown in figure 37 . the current is inversely simultaneous sampling with multiple ads1672s in proportional to the resistor value. figure 18 and multichannel systems. all devices to be synchronized figure 20 (in the typical characteristics) show power must use a common clk input. and typical performance at values of r bias for different clk frequencies. notice that the analog it is recommended that the start pin be aligned to current can be reduced when using a slower the falling edge of clk to ensure proper frequency clk input because the modulator has synchronization because the start signal is more time to settle. avoid adding any capacitance in internally latched by the ads1672 on the rising edge parallel to r bias , because this additional capacitance of clk. interferes with the internal circuitry used to set the biasing. with the clk inputs running, pulse start on the falling edge of clk, as shown in figure 36 . afterwards, the converters operate synchronously with the drdy outputs updating simultaneously. after synchronization, drdy is held high until the digital filter has fully settled. figure 37. external resistor used to set analog power dissipation (depends on f clk ) power down ( pdwn) when not in use, the ads1672 can be powered down by taking the pdwn pin low. all circuitry shuts down, including the voltage reference. to minimize the digital current during power down, stop the clock signal supplied to the clk input. make sure to allow time for the reference to start up after exiting power-down mode. after the reference has stabilized, allow for the modulator and digital filter to settle before retrieving data. figure 36. synchronizing multiple converters copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads1672 r bias rbias agnd ads1672 start 1 ads1672 1 clk drdy drdy 1 start clk start 2 ads1672 2 clk drdy drdy 2 start clk drdy 1 drdy 2 t settle
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com power supplies blank two supplies are used on the ads1672: analog power-supply pins 53 and 54 are used to drive (avdd) and digital (dvdd). each supply must be internal clock supply circuits and, as a result, are suitably bypassed to achieve the best performance. it generally very noisy. it is highly recommended that is recommended that a 1 m f and 0.1 m f ceramic traces from these pins not be shared or run close to capacitor be placed as close to each supply pin as any of the adjacent avdd or agnd pins of the possible. connect each supply-pin bypass capacitor ads1672. these pins should be well-decoupled, to the associated ground. each main supply bus using a 0.1 m f ceramic capacitor placed close to the should also be bypassed with a bank of capacitors pins, and immediately terminated into the power and from 47 m f to 0.1 m f. figure 38 illustrates the ground planes. recommended method for ads1672 power-supply decoupling. figure 38. power-supply decoupling 24 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 +5v 0.1 f m 10 f m +3v +5v 0.1 f m 10 f m 12 3 6 7 9 1011 12 4847 dvdd dgnd avdd agnd agnd agnd avdd agnd agnd avdd avdd 58 17 18 19 20 23 24 25 26 27 31 ads1672 57 56 54 53 avdd agnd agnd dvdd dvdd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dvdd agnd avdd 52 51 dvdd dgnd 50 49 dgnd dvdd 0.1 f m 0.1 f m 0.1 f m 10 f m 0.1 f m 10 f m
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 applications information across the vrefp and vrefn pins. the driving to obtain the specified performance from the amplifier must be able to provide this current as ads1672, the following layout and component well as another 1ma caused by switching at guidelines should be considered. 20mhz. it is therefore recommended that the 1. power supplies: the device requires two power driving amplifier be able to provide at least 5ma, supplies for operation: dvdd and avdd. for and enough decoupling capacitors be installed to both supplies, use a 10 m f tantalum capacitor, attenuate instantaneous current spikes seen at bypassed with a 0.1 m f ceramic capacitor, placed 20mhz. close to the device pins. alternatively, a single 6. analog inputs: the analog input pins must be 10 m f ceramic capacitor can be used. the driven differentially to achieve specified supplies should be relatively free of noise and performance. a true differential driver or should not be shared with devices that produce transformer (ac applications) can be used for this voltage spikes (such as relays, led display purpose. route the analog inputs tracks (ainp, drivers, etc.). if a switching power supply source ainn) as a pair from the buffer to the converter is used, the voltage ripple should be low ( < 2mv). using short, direct tracks and away from digital the power supplies may be sequenced in any tracks. a 750pf capacitor should be used directly order. across the analog input pins, ainp and ainn. a 2. ground plane: a single ground plane connecting low-k dielectric (such as cog or film type) should both agnd and dgnd pins can be used. if be used to maintain low thd. capacitors from separate digital and analog grounds are used, each analog input to ground should be used. connect the grounds together at the converter. they should be no larger than 1/10 the size of the difference capacitor (typically 100pf) to 3. digital inputs: source terminate the digital inputs preserve the ac common-mode performance. to the device with 50 ? series resistors. the resistors should be placed close to the driving 7. component placement: place the power supply, end of the digital source (oscillator, logic gates, analog input, and reference input bypass dsp, etc.) these resistors help reduce ringing on capacitors as close as possible to the device the digital lines, which may lead to degraded pins. this placement is particularly important for adc performance. the small-value ceramic capacitors. surface-mount components are recommended to 4. analog/digital circuits: place analog circuitry avoid the higher inductance of leaded (input buffer, reference) and associated tracks components. together, keeping them away from digital circuitry (dsp, microcontroller, logic). avoid crossing figure 39 to figure 41 illustrate basic connections digital tracks across analog tracks to reduce and interfaces that can be used with the ads1672. noise coupling and crosstalk. the ths4520 and ths4503 are good input drivers 5. reference inputs: use a minimum 10 m f for the ads1672. the ths4520 is a single-supply, tantalum with a 0.1 m f ceramic capacitor directly high-speed, low-power, fully differential amplifier. the across the reference inputs, vrefp and vrefn. ths4503 is a high-speed, bipolar, fully differential the reference input should be driven by a amplifier. the wider supply range of the ths4503 low-impedance source. for best performance, the provides better thd and sfdr performance over the reference should have less than 3 m v rms entire input range of the converter, while sacrificing broadband noise. for references with higher noise. the ths4520 offers comparable performance noise, external reference filtering may be with lower power and higher noise performance. necessary. the ads1672 has 800 of resistance copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads1672
ads1672 sbas402d ? june 2008 ? revised july 2010 www.ti.com figure 39. basic analog signal connection figure 41. basic single-ended input signal figure 40. basic differential input signal interface interface 26 submit documentation feedback copyright ? 2008 ? 2010, texas instruments incorporated product folder link(s): ads1672 differentialinputs 45 8 ainnainp rbias 64 ads1672 63 62 61 60 vrefp vrefp cap2 vrefn vrefn 59 cap1 55 clk 1 f m 7.5k w 750pf 100pf100pf 10 w 10 w 10 f m 0.1 f m 1 f m 20mhz clock source vcm 13 100 w +5v +5v 22 f m 22 f m 100 f m 0.1 f m ref5030 100 w 1k w 10nf opa211 1 f m vinn vinp out vin trim r g 383 w r g 383 w r f 392 w v signal r t 54.9 w r s 50 w r t 54.9 w cm 2.5v r f 392 w r s 50 w vinnvinp - + - + ths4520 cm 2.5v cm 2.5v cm 2.5v 5v cm 2.5v r g 392 w r f 392 w cm 2.5v vinnvinp - + - + ths4520 r g 392 w r f 392 w v in+ v in - 5v
ads1672 www.ti.com sbas402d ? june 2008 ? revised july 2010 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (june, 2009) to revision d page ? changed thd performance from ? 115db to ? 113db in features list .................................................................................. 1 ? revised description text to reflect 86db stop band attenuation ........................................................................................... 1 ? updated total harmonic distortion parameter typical specification for f in = 10khz, ? 6dbfs to ? 113db from ? 118db ......... 3 ? changed stop band attenuation typical specification from 115db to 86db .......................................................................... 3 ? revised figure 1 to show correct sclk and drdy timing sequence ................................................................................. 7 ? revised description ot t drsclk timing .................................................................................................................................... 7 ? deleted previously numbered figures 6, 7, and 9 ................................................................................................................ 9 ? revised figure 8 ................................................................................................................................................................... 9 ? updated figure 9 .................................................................................................................................................................. 9 ? changed figure 10 to more closely represent actual device performance ........................................................................ 10 ? revised figure 12 ............................................................................................................................................................... 10 ? added paragraph about switched-capacitor circuitry and figure 22 to analog inputs (ainp, ainn) section .................... 14 ? revised reference inputs discussion; added statements about requirements of driving amplifier ................................... 25 changes from revision b (november, 2008) to revision c page ? added test condition to integral nonlinearity parameter ....................................................................................................... 3 ? deleted typical specification for offset error parameter ....................................................................................................... 3 ? revised last sentence of common-mode voltage (vcm) section. ..................................................................................... 15 ? updated figure 36 .............................................................................................................................................................. 23 copyright ? 2008 ? 2010, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads1672
package option addendum www.ti.com 3-jun-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) ads1672ipag active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr request free samples ADS1672IPAGG4 active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr request free samples ads1672ipagr active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr purchase samples ads1672ipagrg4 active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr purchase samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads1672ipagr tqfp pag 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads1672ipagr tqfp pag 64 1500 367.0 367.0 45.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2
mechanical data mtqf006a january 1995 revised december 1996 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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